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PRELIMINARY
W48S87-04
Spread Spectrum 3 DIMM Desktop Clock
Features
* Outputs -- 4 CPU Clock (2.5V or 3.3V, 50 to 83.3 MHz) -- 7 PCI (3.3V) -- 1 48-MHz for USB (3.3V) -- 1 24-MHz for Super I/O (3.3V) -- 2 REF (3.3V) -- 1 IOAPIC (2.5V or 3.3V) -- 12 SDRAM * Serial data interface provides additional frequency selection, individual clock output disable, and other functions * Smooth transition supports dynamic frequency assignment * Frequency selection not affected during power down/up cycle * Supports a variety of power-saving options * 3.3V operation * Available in 48-pin SSOP (300 mils)
Key Specifications
0.5% Spread Spectrum Modulation: ......................... 0.5% Jitter (Cycle-to-Cycle): .................................................250 ps Duty Cycle: ................................................................ 45-55% CPU-PCI Skew: ........................................................ 1 to 4 ns PCI-PCI or CPU-CPU Skew: .......................................250 ps Table 1. Pin Selectable Frequency[1] Input Address FS2 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 CPU, SDRAM Clocks (MHz) 50.0 75.0 83.3 68.5 55.0 75.0 60.0 66.8 PCI Clocks (MHz) 25.0 32.0 41.65 34.25 27.5 37.5 30.0 33.4
Block Diagram
SDATA SCLOCK Serial Port Device Control PLL Ref Freq X1 X2 CPU3.3#_2.5 FS0 FS1 FS2 XTAL OSC CPU Clock Mode Control Freq Select I/O MODE VDDL1 IOAPIC PLL1 VDDL2 Stop Clock Cntrl CPU_STOP# /2 4 CPU0:3 VDD3 12 SDRAM0:11 VDD2 I/O I/O 4 PCI_F/FS1 PCI0/FS2 PCI1:4 PCI5(PWR_DWN#) VDD1 I/O I/O 48MHZ/FS0 24MHZ/MODE VDD1 REF0/CPU3.3#_2.5 REF1(CPU_STOP#)
Pin Configuration [2]
VDD1 REF0/CPU3.3#_2.5 GND X1 X2 VDD2 PCI_F/FS1 PCI0/FS2 GND PCI1 PCI2 PCI3 PCI4 VDD2 PCI5(PWR_DWN#) GND SDRAM11 SDRAM10 VDD3 SDRAM9 SDRAM8 GND SDATA SCLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDL1 IOAPIC REF1(CPU_STOP#) GND CPU0 CPU1 VDDL2 CPU2 CPU3 GND SDRAM0 SDRAM1 VDD3 SDRAM2 SDRAM3 GND SDRAM4 SDRAM5 VDD3 SDRAM6 SDRAM7 GND 48MHZ/FS0 24MHZ/MODE
W48S87-04
PWR_DWN#
Power Down Control /2 PLL2 /4
MODE
Notes: 1. Additional frequency selections provided by serial data interface; refer to Table 5 on page 10. 2. Signal names in parenthesis denotes function is selectable through mode pin register strapping.
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 October 19, 1999, rev. **
PRELIMINARY
Pin Definitions
Pin Name CPU0:3 Pin No. 44, 43, 41, 40 Pin Type O Pin Description
W48S87-04
CPU Clock Outputs 0 through 3: These four CPU clock outputs are controlled by the CPU_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDL2 and output characteristics are adjusted by input CPU3.3#_2.5. Fixed PCI Clock Output and Frequency Selection Bit 1: As an output, this pin works in conjunction with PCI0:5. Output voltage swing is controlled by voltage applied to VDD2. When an input, this pin functions as part of the frequency selection address. The value of FS0:2 determines the power-up default frequency of device output clocks as per the Table 1, "Pin Selectable Frequency" on page 1.
PCI_F/FS1
7
I/O
PCI0/FS2
8
I/O
PCI Bus Clock Output 0 and Frequency Selection Bit 2: As an output, this pin works in conjunction with PCI1:5 and PCI_F. Output voltage swing is controlled by voltage applied to VDD2. When an input, this pin functions as part of the frequency selection address. The value of FS0:2 determines the power-up default frequency of device output clocks as per the Table 1, "Pin Selectable Frequency" on page 1.
PCI1:4 PCI5(PWR_DWN#)
10, 11, 12, 13 15
O I/O
PCI Bus Clock Outputs 1 through 4: Output voltage swing is controlled by voltage applied to VDD2. PCI Bus Clock Output 5 or Power-Down Control: As an output, this pin works in conjunction with PCI0:4 and PCI_F. Output voltage swing is controlled by voltage applied to VDD2. If programmed as an input (refer to MODE pin description), this pin is used for power-down control. When LOW, the device goes into a low-power standby condition. All outputs are actively held LOW while in power-down. CPU, SDRAM, and PCI clock outputs are stopped LOW after completing a full clock cycle (2-4 CPU clock cycle latency). When brought HIGH, CPU, SDRAM, and PCI outputs start with a full clock cycle at full operating frequency (3 ms maximum latency).
SDRAM0:11
38, 37, 35, 34, 32, 31, 29, 28, 21, 20, 18, 17 47 26
O
SDRAM Clock Outputs 0 through 11: These twelve SDRAM clock outputs run synchronous to the CPU clock outputs. Output voltage swing is controlled by voltage applied to VDD3. I/O APIC Clock Output: Provides 14.318-MHz fixed frequency. The output voltage swing is controlled by VDDL1. 48-MHz Output and Frequency Selection Bit 0: Fixed clock output that defaults to 48 MHz following device power-up. Output voltage swing is controlled by voltage applied to VDD1. When an input, this pin functions as part of the frequency selection address. The value of FS0:2 determines the power-up default frequency of device output clocks as per the Table 1, "Pin Selectable Frequency" on page 1.
IOAPIC 48MHZ/FS0
O I/O
24MHZ/MODE
25
I/O
24-MHz Output and Mode Control Input: Fixed clock output that defaults to 24 MHz following device power-up. Output voltage swing is controlled by voltage applied to VDD1. When an input, this pin is used for pin programming selection. It determines the functions for pins 15 and 46: MODE 0 1 Pin 15 PWR_DWN# (input) PCI5 (output) Pin 46 CPU_STOP# (input) REF1 (output)
2
PRELIMINARY
Pin Definitions (continued)
Pin Name REF0/CPU3.3#_2.5 Pin No. 2 Pin Type I/O Pin Description
W48S87-04
Fixed 14.318-MHz Output 0 and CPU Output Voltage Swing Selection Input: As an output, this pin is used for various system applications. Output voltage swing is controlled by voltage applied to VDD1. REF0 is stronger than REF1 and should be used for driving ISA slots. When an input, this pin selects the CPU clock output buffer characteristics that are optimized for either 3.3V or 2.5V operation. CPU3.3#_2.5 0 1 VDDQ2 Voltage (CPU0:3 Swing) 3.3V 2.5V
This input adjusts CPU clock output impedance so that a nominal 20 output impedance is maintained. This eliminates or reduces the need to adjust external clock tuning components when changing VDDL2 voltage. CPU clock phase is also adjusted so that both CPU and SDRAM and CPU-to-PCI clock skew is maintained over the two VDDL2 voltage options. This input does not adjust IOAPIC clock output characteristics. REF1(CPU_Stop#) 46 I/O Fixed 14.318-MHz Output 0 or CPU Clock Output Stop Control: Used for various system applications. Output voltage swing is controlled by voltage applied to VDD1. REF0 is stronger than REF1 and should be used for driving ISA slots. If programmed as an input (refer to MODE pin description), this pin is used for stopping the CPU clock outputs. When brought LOW, clock outputs CPU0:3 are stopped LOW after completing a full clock cycle (2-3 CPU clock latency). When brought HIGH, clock outputs CPU0:3 are starting beginning with a full clock cycle (2-3 CPU clock latency). X1 4 I Crystal Connection or External Reference Frequency Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. Crystal Connection: An input connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. Serial Data Input: Data input for Serial Data Interface. Refer to Serial Data Interface section that follows. Serial Clock Input: Clock input for Serial Data Interface. Refer to Serial Data Interface section that follows. Power Connection: Power supply for crystal oscillator and REF0:1 output buffers. Connected to 3.3V supply. Power Connection: Power supply for PCI clock output buffers. Connected to 3.3V supply. Power Connection: Power supply for IOAPIC output buffer. Connected to 2.5V or 3.3V supply. Power Connection: Power supply for CPU clock output buffers. Connected to 2.5V or 3.3V supply. Power Connection: Power supply for SDRAM clock output buffers. Connected to 3.3V supply. Ground Connection: Connect all ground pins to the common system ground plane.
X2 SDATA SCLOCK VDD1 VDD2 VDDL1 VDDL2 VDD3 GND
5 23 24 1 6,14 48 42 19, 30, 36 3, 9, 16, 22, 27, 33, 39, 45
I I I P P P P P G
3
PRELIMINARY
Overview
The W48S87-04, a motherboard clock synthesizer, can provide either a 2.5V or 3.3V CPU clock swing, making it suitable for a variety of CPU options. Twelve SDRAM clocks are provided in phase with the CPU clock outputs. This provides clock support for up to three SDRAM DlMMs. Fixed output frequency clocks are provided for other system functions.
W48S87-04
I/O pins are three-stated, allowing the output strapping resistor on each l/O pin to pull the pin and its associated capacitive clock load to either a logic HIGH or LOW state. At the end of the 2-ms period, the established logic 0 or 1 condition of each l/O is pin is then latched. Next the output buffers are enabled, which converts the l/O pins into operating clock outputs. The 2-ms timer is started when VDD reaches 2.0V. The input bits can only be reset by turning VDD off and then back on again. It should be noted that the strapping resistors have no significant effect on clock output signal integrity. The drive impedance of both clock outputs is <40 (nominal) which is minimally affected by the 10-k strap to ground or VDD. As with the series termination resistor, the output strapping resistor should be placed as close to the l/O pin as possible in order to keep the interconnecting trace short. The trace from the resistor to ground or VDD should be kept less than two inches in length to prevent system noise coupling during input logic sampling. When the clock outputs are enabled following the 2-ms input period, target (normal) output frequency is delivered assuming that VDD has stabilized. If VDD has not yet reached full value, output frequency initially may be below target but will increase to target once VDD voltage has stabilized. In either case, a short output clock cycle may be produced from the CPU clock outputs when the outputs are enabled.
VDD Output Strapping Resistor Series Termination Resistor 22 Clock Load
Functional Description
I/O Pin Operation Pins 2, 7, 8, 25, and 26 are dual-purpose l/O pins. Upon powerup these pins act as logic inputs, allowing the determination of assigned device functions. A short time after power-up, the logic state of these pins is latched and the pins then become clock outputs. This feature reduces device pin count by combining clock outputs with input select pins. An external 10-k "strapping" resistor is connected between each l/O pin and ground or VDD3. Connection to ground sets a latch to "0", connection to V DD3 sets a latch to "1". Figure 1 and Figure 2 show two suggested methods for strapping resistor connection. Upon W48S87-04 power-up, the first 2 ms of operation is used for input logic selection. During this period, these dual-purpose
10 k (Load Option 1) W48S87-04 Output Buffer Power-on Reset Timer Output Three-state Hold Output Low
D
10 k (Load Option 0)
Q
Data Latch
Figure 1. Input Logic Selection Through Resistor Load Option
Jumper Options
VDD 10 k W48S87-04 Output Buffer Power-on Reset Timer Output Three-state Hold Output Low
D
Output Strapping Resistor Series Termination Resistor R Clock Load
Resistor Value R Output 39 IOAPIC, SDRAM All other clock outputs 33
Q
Data Latch
Figure 2. Input Logic Selection Through Jumper Option
4
PRELIMINARY
CPU/PCI Frequency Selection CPU frequency is selected with I/O pins 26, 7, and 8 (48MHz/FS0, PCI_F/FS1, and PCI0/FS2, respectively). Refer to Table 1 for CPU/PCI frequency programming information. Additional frequency selections are available through the serial data interface. Refer to Table 5 on page 10. Output Buffer Configuration Clock Outputs All clock outputs are designed to drive serial terminated clock lines. The W48S87-04 outputs are CMOS-type, which provide rail-to-rail output swing. To accommodate the limited voltage swing required by some processors, the output buffers of CPU0:3 use a special VDDL2 power supply pin that can be tied to 2.5V nominal. Crystal Oscillator The W48S87-04 requires one input reference clock to synthesize all output frequencies. The reference clock can be either an externally generated clock signal or the clock generated by
W48S87-04
the internal crystal oscillator. When using an external clock signal, pin X1 is used as the clock input and pin X2 is left open. The input threshold voltage of pin X1 is VDD/2. The internal crystal oscillator is used in conjunction with a quartz crystal connected to device pins X1 and X2. This forms a parallel resonant crystal oscillator circuit. The W48S87-04 incorporates the necessary feedback resistor and crystal load capacitors. Including typical stray circuit capacitance, the total load presented to the crystal is approximately 20 pF. For optimum frequency accuracy without the addition of external capacitors, a parallel-resonant mode crystal specifying a load of 20 pF should be used. This will typically yield reference frequency accuracies within 100 ppm. Dual Supply Voltage Operation The W48S87-04 is designed for dual power supply operation. Supply pins VDD1, VDD2, and VDD3 are connected to a 3.3V supply and supply power to the internal core circuit and to the clock output buffers, except for outputs CPU0:3 and IOAPIC. Supply pins VDDL1 and VDDL2 may be connected to either a 2.5V or 3.3V supply.
5
PRELIMINARY
Spread Spectrum Generator
The device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. By increasing the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. This effect is depicted in Figure 3. As depicted in Figure 3, a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. The reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. The equation for the reduction is dB = 6.5 + 9*log10(P) + 9*log10(F) Where P is the percentage of deviation and F is the frequency in MHz where the reduction is measured.
5dB/div
W48S87-04
The output clock is modulated with a waveform depicted in Figure 4. This waveform, as discussed in "Spread Spectrum Clock Generation for the Reduction of Radiated Emissions" by Bush, Fessler, and Hardin produces the maximum reduction in the amplitude of radiated electromagnetic emissions. The deviation selected for this chip is 0.5% of the center frequency. Figure 4 details the Cypress spreading pattern. Cypress does offer options with more spread and greater EMI reduction. Contact your local Sales representative for details on these devices. Spread Spectrum clocking is activated or deactivated by selecting the appropriate values for bits 1-0 in data byte 0 of the I2C data stream. Refer to Table 4 for more details.
SSFTG
Typical Clock
Amplitude (dB)
-SS%
Frequency Span (MHz)
+SS%
+1.0
Figure 3. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
MAX (+.0.5%)
FREQUENCY
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
10%
20%
30%
40%
50%
60%
70%
80%
90%
MIN. (-0.5%)
Figure 4. Typical Modulation Profile
6
100%
PRELIMINARY
Serial Data Interface
The W48S87-04 features a two-pin, serial data interface that can be used to configure internal register settings that control particular device functions. Upon power-up, the W48S87-04 initializes with default register settings, therefore the use of this serial data interface is optional. The serial interface is writeonly (to the clock chip) and is the dedicated function of device pins SDATA and SCLOCK. In motherboard applications, SDATA and SCLOCK are typically driven by two logic outputs Table 2. Serial Data Interface Control Functions Summary Control Function Clock Output Disable Description
W48S87-04
of the chipset. Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management functions. Table 2 summarizes the control functions of the serial data interface. Operation Data is written to the W48S87-04 in ten bytes of eight bits each. Bytes are written in the order shown in Table 3.
Common Application
Any individual clock output(s) can be disabled. Dis- Unused outputs are disabled to reduce EMI abled outputs are actively held LOW. and system power. Examples are clock outputs to unused SDRAM DIMM socket or PCI slot. Provides CPU/PCI frequency selections beyond the 50- and 66.8-MHz selections that are provided by the FS0:2 power-on default selection. Frequency is changed in a smooth and controlled fashion. Puts all clock outputs into a high-impedance state. All clock outputs toggle in relation with X1 input, internal PLL is bypassed. Refer to Table 4. For alternate CPU devices, and power management options. Smooth frequency transition allows CPU frequency change under normal system operation. Production PCB testing. Production PCB testing.
CPU Clock Frequency Selection
Output Three-state Test Mode (Reserved)
Reserved function for future device revision or pro- No user application. Register bit must be writduction device testing. ten as 0.
Table 3. Byte Writing Sequence Byte Sequence 1 Byte Name Slave Address Bit Sequence 11010010 Byte Description Commands the W48S87-04 to accept the bits in Data Bytes 0-6 for internal register configuration. Since other devices may exist on the same common serial data bus, it is necessary to have a specific slave address for each potential receiver. The slave receiver address for the W48S87-04 is 11010010. Register setting will not be made if the Slave Address is not correct (or is for an alternate slave receiver). Unused by the W48S87-04, therefore bit values are ignored ("don't care"). This byte must be included in the data write sequence to maintain proper byte allocation. The Command Code Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. Unused by the W48S87-04, therefore bit values are ignored ("don't care"). This byte must be included in the data write sequence to maintain proper byte allocation. The Byte Count Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. The data bits in these bytes set internal W48S87-04 registers that control device operation. The data bits are only accepted when the Address Byte bit sequence is 11010010, as noted above. For description of bit control functions, refer to Table 4, Data Byte Serial Configuration Map.
2
Command Code
Don't Care
3
Byte Count
Don't Care
4 5 6 7 8 9 10
Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3 Data Byte 4 Data Byte 5 Data Byte 6
Refer to Table 4
7
PRELIMINARY
Writing Data Bytes Each bit in the data bytes control a particular device function except for the "reserved" bits which must be written as a logic 0. Bits are written MSB (most significant bit) first, which is bit Table 4. Data Bytes 0-6 Serial Configuration Map Affected Pin Bit(s) 7 6 5 4 3 Pin No. ----Pin Name ----Control Function (Reserved) BYT0_SEL2 BYT0_SEL1 BYT0_SEL0 BYT0 _FS# Frequency Controlled by FS (2:0) 0 -Refer to Table 5 Refer to Table 5 Refer to Table 5 Frequency Controlled by BYT0_SEL (2:0) Data Byte 0 -Bit Control 1
W48S87-04
7. Table 4 gives the bit formats for registers located in Data Bytes 0-6. Table 5 details additional frequency selections that are available through the serial data interface. Table 6 details the select functions for Byte 0, bits 1 and 0.
Default 0 0 0 0 0
2 1-0
22 ---
(Reserved) Bit 1 0 0 1 1 Bit 0 0 1 0 1 Function (See Table 6 for function details) Normal Operation Test Mode Spread Spectrum On All Outputs Three-stated Low Low --Low Low Low Low -Low Low Low Low Low Low Low Active Active --Active Active Active Active -Active Active Active Active Active Active Active
0 00
Data Byte 1 7 6 5 4 3 2 1 0 Data Byte 2 7 6 5 4 3 2 1 0 -7 15 13 12 11 10 8 -PCI_F PCI5 PCI4 PCI3 PCI2 PCI1 PCI0 (Reserved) Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable 0 1 1 1 1 1 1 1 26 25 --40 41 43 44 48MHZ 24MHZ --CPU3 CPU2 CPU1 CPU0 Clock Output Disable Clock Output Disable (Reserved) (Reserved) Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable 1 1 0 0 1 1 1 1
8
PRELIMINARY
Table 4. Data Bytes 0-6 Serial Configuration Map (continued) Affected Pin Bit(s) 7 6 5 4 3 2 1 0 Data Byte 4 7 6 5 4 3 2 1 0 Data Byte 5 7 5 5 4 3 2 1 0 Data Byte 6 7 6 5 4 3 2 1 0 ----------------(Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) -------------------47 --46 2 ---IOAPIC --REF1 REF0 (Reserved) (Reserved) (Reserved) Clock Output Disable (Reserved) (Reserved) Clock Output Disable Clock Output Disable ---Low --Low Low ---Active --Active Active ----17 18 20 21 ----SDRAM11 SDRAM10 SDRAM9 SDRAM8 (Reserved) (Reserved) (Reserved) (Reserved) Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable ----Low Low Low Low ----Active Active Active Active Pin No. 28 29 31 32 34 35 37 38 Pin Name SDRAM7 SDRAM6 SDRAM5 SDRAM4 SDRAM3 SDRAM2 SDRAM1 SDRAM0 Control Function Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable 0 Low Low Low Low Low Low Low Low Data Byte 3 Active Active Active Active Active Active Active Active Bit Control 1
W48S87-04
Default 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0
9
PRELIMINARY
Table 5. Additional Frequency Selections through Serial Data Interface Data Bytes Input Conditions Data Byte 0, Bit 3 = 1 Bit 6 BYT0_SEL2 0 0 0 0 1 1 1 1 Bit 5 BYT0_SEL1 0 0 1 1 0 0 1 1 Bit 4 BYT0_SEL0 0 1 0 1 0 1 0 1 CPU, SDRAM Clocks (MHz) 50 75.0 83.3 68.5 55.0 75.0 60.0 66.8
W48S87-04
Output Frequency PCI Clocks (MHz) 25 32 41.65 34.25 27.5 37.5 30.0 33.4
Table 6. Select Function for Data Byte 0, Bits 0:1 Input Conditions Data Byte 0 Function Normal Operation Test Mode Spread Spectrum Three-state Bit 1 0 0 1 1 Bit 0 0 1 0 1 CPU0:3, SRAM0:11 Note 3 X1/2 Note 3 SS0.5% Hi-Z Output Conditions PCI_F, PCI0:5 Note 3 X1/4 Note 3 SS0.5% Hi-Z REF0:1, IOAPIC 14.318 MHz X1 14.318 MHz Hi-Z 48/24MHZ 48/24 MHz Note 4 48/24 MHz Hi-Z
Note: 3. CPU, SDRAM, and PCI frequency selections are listed in Table 1 and Table 5. 4. In Test Mode, the 48/24MHz clock outputs are: - X1/2 for 48-MHz output. - X1/4 for 24-MHz output.
10
PRELIMINARY
How To Use the Serial Data Interface
Electrical Requirements Figure 5 illustrates electrical characteristics for the serial interface bus used with the W48S87-04. Devices send data over the bus with an open drain logic output that can (a) pull the bus line LOW, or (b) let the bus default to logic 1. The pull-up resistors on the bus (both clock and data lines) establish a default logic 1. All bus devices generally have logic inputs to receive data.
VDD
W48S87-04
Although the W48S87-04 is a receive-only device (no data write-back capability), it does transmit an "acknowledge" data pulse after each byte is received. Thus, the SDATA line can both transmit and receive data. The pull-up resistor should be sized to meet the rise and fall times specified in AC parameters, taking into consideration total bus line capacitance.
VDD
~ 2k SERIAL BUS DATA LINE SERIAL BUS CLOCK LINE
~ 2k
SDCLK CLOCK IN CLOCK OUT N DATA IN DATA OUT
SDATA CLOCK IN N
SCLOCK DATA IN DATA OUT
SDATA
N
CHIP SET (SERIAL BUS MASTER TRANSMITTER)
CLOCK DEVICE (SERIAL BUS SLAVE RECEIVER)
Figure 5. Serial Interface Bus Electrical Characteristics
11
PRELIMINARY
Signaling Requirements As shown in Figure 6, valid data bits are defined as stable logic 0 or 1 condition on the data line during a clock HIGH (logic 1) pulse. A transitioning data line during a clock HIGH pulse may be interpreted as a start or stop pulse (it will be interpreted as a start or stop pulse if the start/stop timing parameters are met). A write sequence is initiated by a "start bit" as shown in Figure 7. A "stop bit" signifies that a transmission has ended. As stated previously, the W48S87-04 sends an "acknowledge" pulse after receiving eight data bits in each byte as shown in Figure 8. Sending Data to the W48S87-04
W48S87-04
The device accepts data once it has detected a valid start bit and address byte sequence. Device functionality is changed upon the receipt of each data bit (registers are not double buffered). Partial transmission is allowed meaning that a transmission can be truncated as soon as the desired data bits are transmitted (remaining registers will be unmodified). Transmission is truncated with either a stop bit or new start bit (restart condition).
SDATA
SCLOCK
Valid Data Bit
Change of Data Allowed
Figure 6. Serial Data Bus Valid Data Bit
SDATA
SCLOCK Start Bit Stop Bit
Figure 7. Serial Data Bus Start and Stop Bit
12
Figure 8. Serial Data Bus Write Sequence
Signaling from System Core Logic Start Condition Slave Address (First Byte)
SDATA MSB 1 1 0 1 0 0 LSB 1 0 MSB
Stop Condition Command Code (Second Byte)
LSB
Byte Count (Third Byte)
MSB MSB
Last Data Byte (Last Byte)
LSB
SCLOCK
1
2
3
4
5
6
7
8
A
1
2
3
4
5
6
7
8
A
1
2
3
4
1
2
3
4
5
6
7
8
A
PRELIMINARY
SDATA
Signaling by Clock Device
Acknowledgment Bit from Clock Device
13 Figure 9. Serial Data Bus Timing Diagram
SDATA tSPF tLOW SCLOCK tSTHD tR tHIGH tF tDSU tDHD tSP tSPSU tSTHD t SPSU
W48S87-04
PRELIMINARY
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions
.
W48S87-04
above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Rating -0.5 to +7.0 -65 to +150 0 to +70 -55 to +125 2 (min.) Unit V C C C kV
Parameter VDD, VIN TSTG TA TB ESDPROT Crystal Oscillator Parameter VTH CLOAD CIN,X1 Description X1 Input Threshold Voltage
Description Voltage on any pin with respect to GND Storage Temperature Operating Temperature Ambient Temperature under Bias Input ESD Protection
Test Condition
[5]
Min.
Typ. 1.65 20
Max.
Unit V pF pF
Load Capacitance, Imposed on External Crystal[6] X1 Input Capacitance[7] Pin X2 unconnected
40
3.3V DC Electrical Characteristics (CPU3.3#_2.5 Input = 0)
TA = 0C to +70C, VDD1:3 = VDDL1:2 = 3.3V5% (3.135-3.465V) Parameter Supply Current IDD Combined 3.3V Supply Current CPU0:3 =66.8 MHz Outputs Loaded[8] 160 mA Description Test Condition Min. Typ. Max. Unit
Logic Inputs (All referenced to VDDQ3 = 3.3V) VIL VIH IIL IIH VOL VOH IOL Input Low Voltage Input High Voltage Input Low Current
[9] [9]
0.8 2.0 10 10 IOL = 1 mA IOH = -1 mA CPU0:3
[10]
V V A A mV V mA
Input High Current
Clock Outputs Output Low Voltage Output High Voltage Output Low Current SDRAM0:11 PCI_F, PCI0:5 IOAPIC REF0 REF1 48/24MHZ 50 3.1 55 80 55 100 60 45 55 75 110 75 135 75 60 75 105 155 105 190 90 75 105
VOL = 1.5V
Notes: 5. X1 input threshold voltage (typical) is VDD/2. 6. The W48S87-04 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 20 pF; this includes typical stray capacitance of short PCB traces to crystal. 7. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected). 8. All clock outputs loaded with maximum lump capacitance test load specified in AC Electrical Characteristics section. 9. W48S87-04 logic inputs have internal pull-up devices. 10. CPU0:3 loaded by 60, 6-inch long transmission lines ending with 20-pF capacitors.
14
PRELIMINARY
3.3V DC Electrical Characteristics (CPU3.3#_2.5 Input = 0) (continued)
TA = 0C to +70C, VDD1:3 = VDDL1:2 = 3.3V5% (3.135-3.465V) Parameter IOH Description Output High Current CPU0:3
[10]
W48S87-04
Test Condition VOH = 1.5V
Min. 55 80 55 100 60 45 55
Typ. 85 120 85 150 85 65 85
Max. 125 175 125 220 110 90 125 5 6 7
Unit mA
SDRAM0:11 PCI_F, PCI0:5 IOAPIC REF0 REF1 48/24MHZ Pin Capacitance/Inductance CIN COUT LIN VIL VIH IIL IIH IOL CIN CSDATA CSCLOCK Input Pin Capacitance Output Pin Capacitance Input Pin Inductance Input Low Voltage Input High Voltage Input Low Current Input High Current Sink Current into SDATA, Open Drain N-Channel Device On Input Capacitance of SDATA and SCLOCK Total Capacitance of SDATA Bus Total Capacitance of SCLOCK Bus VDD = 3.3V VDD = 3.3V No internal pull-up/down on SCLOCK No internal pull-up/down on SCLOCK IOL = 0.3VDD Except X1 and X2
pF pF nH V V A A mA
Serial Input Port 0.3VDD 0.7VDD 10 10 6 10 400 400
pF pF pF
2.5V DC Electrical Characteristics (CPU3.3#_2.5 Input = 1)
TA = 0C to +70C, VDD1:3 = 3.3V5% (3.135-3.456V), VDDL1:2 = 2.5V5% (2.375-2.625V) Parameter Supply Current IDD-3.3V IDD-2.5 Logic Inputs VIL VIH IIL IIH Input Low Voltage Input High Voltage Input Low Current[9] Input High Current
[9]
Description 3.3V Supply Current 2.5V Supply Current
Test Condition CPU0:3 = 66.4 MHz Outputs Loaded[8] CPU0:3= 66.4 MHz Outputs Loaded[8]
Min.
Typ.
Max. 300 50
Unit mA mA
0.8 2.0 10 10
V V A A
15
PRELIMINARY
2.5V DC Electrical Characteristics (CPU3.3#_2.5 Input = 1) (continued)
TA = 0C to +70C, VDD1:3 = 3.3V5% (3.135-3.456V), VDDL1:2 = 2.5V5% (2.375-2.625V) Parameter Clock Outputs VOL VOH IOL IOH Output Low Voltage Output High Voltage Output Low Current Output High Current CPU0:3 IOAPIC CPU0:3[10] IOAPIC Pin Capacitance/Inductance CIN COUT LIN VIL VIH Input Pin Capacitance Output Pin Capacitance Input Pin Inductance Input Low Voltage Input High Voltage VDD = 2.5V VDD = 2.5V 0.7VDD Except X1 and X2
[10]
W48S87-04
Description
Test Condition IOL = 1 mA IOH = -1 mA VOL = 1.25V VOL = 1.25V VOH = 1.25V VOH = 1.25V
Min.
Typ.
Max. 50
Unit mV V mA mA
2.2 45 55 40 50 70 85 65 80 105 130 95 120 5 6 7 0.3VDD
pF pF nH V V
Serial Input Port
3.3V AC Electrical Characteristics (CPU3.3#_2.5 Input = 0)
TA = 0C to +70C, VDD1:3 = VDD1:3 = 3.3V5% (3.135-3.465V), fXTL = 14.31818 MHz Spread Spectrum function turned off AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output. CPU Clock Outputs, CPU0:3 (Lump Capacitance Test Load = 20 pF) CPU = 66.8 MHz Parameter tP f tH tL tR tF tD tJC Description Period Frequency, Actual High Time Low Time Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Test Condition/Comments Measured on rising edge at 1.5V Determined by PLL divider ratio Duration of clock cycle above 2.4V Duration of clock cycle below 0.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.5V 5.2 5 1 1 45 4 4 55 250 Min. 15 66.8 6 5.8 1 1 45 4 4 55 250 CPU = 60 MHz Typ. Max. Unit ns 59.876 MHz ns ns V/ns V/ns % ps 16.7 Typ. Max. Min.
Output Rise Edge Rate Measured from 0.4V to 2.4V
tSK fST
Output Skew
250 3
250 3
ps ms
Frequency Stabilization Assumes full supply voltage reached within 1 ms from power-up. Short cyfrom Power-up (cold cles exist prior to frequency stabilizastart) tion. AC Output Impedance Average value during switching transition. Used for determining series termination value. 15 20
Zo
30
15
20
30
16
PRELIMINARY
3.3V AC Electrical Characteristics (CPU3.3#_2.5 Input = 0) (continued)
SDRAM Clock Outputs, SDRAM0:11 (Lump Capacitance Test Load = 30 pF) CPU = 66.8 MHz Parameter tP f tR tF tD tJC Description Period Frequency, Actual Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Test Condition/Comments Measured on rising edge at 1.5V Determined by PLL divider ratio 1 1 45 Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.5V Covers all CPU/SDRAM outputs. Measured on rising edge at 1.5V. Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 10 15 100 500 3 Min. 15 66.8 4 4 55 250 1 1 45
W48S87-04
CPU = 60 MHz Typ. Max. Unit ns 59.876 4 4 55 250 MHz V/ns V/ns % ps 16.7
Typ. Max. Min.
Output Rise Edge Rate Measured from 0.4V to 2.4V
tSK tSK fST
Output Skew CPU to SDRAM Clock Skew Frequency Stabilization from Power-up (cold start) AC Output Impedance
100 500 3
ps ps ms
Zo
20
10
15
20
PCI Clock Outputs, PCI_F and PCI0:5 (Lump Capacitance Test Load = 30 pF) CPU = 66.8 MHz Parameter tP f tH tL tR tF tD tJC Description Period Frequency, Actual High Time Low Time Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Test Condition/Comments Measured on rising edge at 1.5V Determined by PLL divider ratio Duration of clock cycle above 2.4V Duration of clock cycle below 0.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.5V 1 12 12 1 1 45 4 4 55 250 Min. 30 33.4 13.3 13.3 1 1 45 4 4 55 250 CPU = 60 MHz Typ. Max. Unit ns 29.938 MHz ns ns V/ns V/ns % ps 33.3 Typ. Max. Min.
Output Rise Edge Rate Measured from 0.4V to 2.4V
tSK tO
Output Skew
250 4 1
250 4
ps ns
CPU to PCI Clock Skew Covers all CPU/PCI outputs. Measured on rising edge at 1.5V. CPU leads PCI output. Frequency Stabilization from Power-up (cold start) AC Output Impedance Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value.
fST
3
3
ms
Zo
15
20
30
15
20
30
17
PRELIMINARY
3.3V AC Electrical Characteristics (CPU3.3#_2.5 Input = 0) (continued)
IOAPIC Clock Output (Lump Capacitance Test Load = 20 pF)
W48S87-04
CPU = 60/66.8 MHz Parameter f tR tF tD fST Description Frequency, Actual Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Frequency generated by crystal oscillator Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 8 12 1 1 45 Min. Typ. 14.31818 4 4 55 1.5 Max. Unit MHz V/ns V/ns % ms
Zo
15
REF0 Clock Output (Lump Capacitance Test Load = 45 pF) CPU = 60/66.8 MHz Parameter f tR tF tD fST Description Frequency, Actual Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Test Condition/Comments Frequency generated by crystal oscillator Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V 1 1 40 Min. Typ. 14.31818 4 4 60 1.5 Max. Unit MHz V/ns V/ns % ms
Frequency Stabilization Assumes full supply voltage reached within from Power-up (cold start) 1 ms from power-up. Short cycles exist prior to frequency stabilization. AC Output Impedance Average value during switching transition. Used for determining series termination value. 17 20
Zo
25
REF1 Clock Output (Lump Capacitance Test Load = 20 pF) CPU = 60/66.8 MHz Parameter f tR tF tD fST Description Frequency, Actual Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Frequency generated by crystal oscillator Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 20 25 1 1 40 Min. Typ. 14.31818 4 4 55 1.5 Max. Unit MHz V/ns V/ns % ms
Zo
35
18
PRELIMINARY
3.3V AC Electrical Characteristics (CPU3.3#_2.5 Input = 0) (continued)
48-/24-MHZ Clock Outputs (Lump Capacitance Test Load = 20 pF)
W48S87-04
CPU = 60/66.8 MHz Parameter f fD m/n tR tF tD tJC Description Frequency, Actual Deviation from 48 MHz PLL Ratio Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Test Condition/Comments Determined by PLL divider ratio (see n/m below) (48.008 - 48)/48 (14.31818 MHz x 57/17 = 48.008 MHz) Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. 1 1 40 Min. Typ. Max. Unit MHz ppm 4 4 55 500 V/ns V/ns % ps 48.008/24.004 +167 57/17
fST
Frequency Stabilization Assumes full supply voltage reached within from Power-up (cold start) 1 ms from power-up. Short cycles exist prior to frequency stabilization. AC Output Impedance Average value during switching transition. Used for determining series termination value. 15 20
3
ms
Zo
30
Serial Input Port Parameter fSCLOCK tSTHD tLOW tHIGH tDSU tDHD tR tF tSTSU tSPF tSP Description SCLOCK Frequency Start Hold Time SCLOCK Low Time SCLOCK High Time Data Setup Time Data Hold Time Rise Time, SDATA and SCLOCK Fall Time, SDATA and SCLOCK Stop Setup Time Bus Free Time between Stop and Start Condition Allowable Noise Spike Pulse Width (Transmitter should provide a 300-ns hold time to ensure proper timing at the receiver.) From 0.3VDD to 0.7VDD From 0.7VDD to 0.3VDD 4.0 4.7 50 Normal Mode Test Condition Min. 0 4.0 4.7 4.0 250 0 1000 300 Typ. Max. 100 Unit kHz s s s ns ns ns ns s s ns
19
PRELIMINARY
2.5V AC Electrical Characteristics (CPU3.3#_2.5 Input = 1)
TA = 0C to +70C, VDD1:3 = 3.3V5% (3.135-3.465V), VDDL1:2 = 2.5V5% (2.375-2.625V), fXTL = 14.31818 MHz Spread Spectrum function turned off
W48S87-04
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output. CPU Clock Outputs, CPU0:3 (Lump Capacitance Test Load = 20 pF) CPU = 66.8 MHz Parameter tP f tH tL tR tF tD tJC Description Period Frequency, Actual High Time Low Time Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Test Condition/Comments Measured on rising edge at 1.25V Determined by PLL divider ratio Duration of clock cycle above 2.0V Duration of clock cycle below 0.4V Measured from 2.0V to 0.4V Measured on rising and falling edge at 1.25V Measured on rising edge at 1.25V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.25V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 12 20 5.2 5 0.8 0.8 45 3 3 55 250 15 66.8 6 5.8 0.8 0.8 45 3 3 55 250 CPU = 60 MHz Typ. Max. Unit ns 59.876 MHz ns ns V/ns V/ns % ps 16.7 Min. Typ. Max. Min.
Output Rise Edge Rate Measured from 0.4V to 2.0V
tSK fST
Output Skew Frequency Stabilization from Power-up (cold start) AC Output Impedance
250 3
250 3
ps ms
Zo
30
12
20
30
IOAPIC Clock Output (Lump Capacitance Test Load = 20 pF) CPU = 60/66.8 MHz Parameter f tR tF tD fST Description Frequency, Actual Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Frequency generated by crystal oscillator Measured from 0.4V to 2.0V Measured from 2.0V to 0.4V Measured on rising and falling edge at 1.25V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 10 15 1 1 45 Min. Typ. 14.31818 4 4 55 1.5 Max. Unit MHz V/ns V/ns % ms
Zo
25
Ordering Information
Ordering Code W48S87 Document #: 38-00859 Freq. Mask Code 04 Package Name H Package Type 48-pin SSOP (300 mils)
20
PRELIMINARY
Package Diagram
48-Pin Small Shrink Outline Package (SSOP, 300 mils)
W48S87-04
Summary of nominal dimensions in inches: Body Width: 0.296 Lead Pitch: 0.025 Body Length: 0.625 Body Height: 0.102
(c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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